1. Field of the Invention
The present invention relates to a semiconductor device with a constant current source circuit which is not influenced by noise.
2. Description of the Related Art
A conventional constant current source circuit 10 is shown in FIG. 1. The conventional constant current source circuit 10 is composed of a constant current source section 11 and an output section 12.
The constant current source section 11 is composed of two N-channel MOS transistors M1 and M2, and two P-channel MOS transistors M3 and M4. The transistor M1 has a source directly connected to the ground (GND), and a gate and a drain connected directly to each other. The transistor M2 is connected at its source via a resistor R1 to the ground, at its gate to the drain of the transistor M1, and at its drain to the drain of the transistor M4. The two P-channel MOS transistors M3 and M4 are connected at their sources commonly to a power supply potential VCC and at their gates to each other. The drain of the transistor M3 is connected directly to the drain and gate of the transistor M1. The drain of the transistor M4 is connected directly to the gate of the transistor M4 and to the drain of the transistor M2. The transistors M3 and M4 form a current mirror circuit for driving the transistors M1 and M2. The transistors M1 to M4 form a Widlar current mirror circuit.
The output section 12 is composed of a P-channel MOS transistor M5. The transistor M5 is connected at its source directly to the power supply potential VCC and at the gate to a node C between the drain of the transistor M2 and the drain of the transistor M4 in the constant current source section 11. An output current Iout is outputted from a node F connected to the drain of the transistor M5.
Next, the operation principle of the constant current source circuit 10 will be described. Supposing that the current at the drain of the transistor M3 is I1 and the current at the drain of the transistor M4 is I2 in the current mirror circuit of the transistors M3 and M4, a ratio between the transistor M3 ratio and the transistor M4 ratio is expressed as I1:I2. The ratio indicates a ratio of the gate widths or the sizes of the transistors. For simplifying the description of the operation principle, it is supposed that the M3 ratio is equal to the M4 ratio, i.e., the transistors M3 and M4 are identical in capability ratio and the M2 ratio is equal to 10 times of the M1 ratio.
FIG. 2 is a graph showing sub-threshold characteristics of the transistors M1 and M2. As seen from FIG. 2, when the same gatexe2x80x94source voltage VGS is applied to the transistors M1 and M2, the transistor M2 flows a current 10 times greater than that of the transistor M1.
As shown in FIG. 2, the voltage V1 at the current I1 of the transistor M1 is equal to the gatexe2x80x94source voltage VGS of the transistor M1. More particularly, the voltage V1 is a voltage at a node B shown in FIG. 1. The voltage V2 at the current 12 of the transistor M2 is equal to the voltage VGS of the transistor M2. More specifically, (voltage V2)=(voltage at node B)xe2x88x92(voltage at a node D). If the voltage difference (V1xe2x88x92V2) is equal to xcex94V, the voltage difference xcex94V is an electromotive force due to the resistor R1, and I2=xcex94V/R1 is satisfied. The voltage difference xcex94V is equal to a sub-threshold coefficient. The sub-threshold coefficient is defined as the voltage difference xcex94VGS necessary to change the current for one digit.
The output current lout is determined as (xcex94V/R1)xc3x97(M5 ratio/M4 ratio). Thus, the current outputted from the constant current circuit becomes a constant current.
It should be noted that the M3 ratio is equal to the M4 ratio for simple description in the above. However, the ratios of the transistors are not limited to them. The output current lout is determined depending on the ratios of the transistors M1 to M5 and the resistance of the resistor R1.
The conventional constant current source circuit 10 described above may be used, for example, in a reference voltage generating circuit shown in FIG. 3. In the reference voltage generating circuit 20, a node F in the constant current source circuit 10 is connected to the ground via a resistor r and a diode D1. An output voltage Vout is outputted from the node F.
As shown in FIG. 2, as the temperature is increased, the inclination of the sub-threshold curves becomes small due to the transistor characteristics. As a result, the sub-threshold coefficient increases. Hence, as the temperature is increased, the voltage difference xcex94V is also increased. This results in the increase of the output current lout from the constant current source circuit 10 so that the electromotive force of the resistor r, i.e., (Vout)xe2x88x92(voltage at node G) is increased. Meanwhile, as the temperature is increased, the built-in potential of the diode D1 becomes low. This results in the decrease of the voltage at the node G in a higher temperature. Thus, the output current Iout is controlled using the ratios of the transistors M1 to M5 and the resistance of the resistors R1 and r so that the influence due to the temperature characteristic can be cancelled. Therefore, the output reference voltage Vout can be obtained free from variations in the temperature. Also, when the resistors R1 and r are formed of the same material at the same time, changes in their resistances caused by the temperature change or the production deviation can be cancelled as shown in FIG. 4.
In a DRAM employing an N-channel transistor as a memory cell transistor, the substrate potential (VBB) of the memory cell transistor is needed to be set to a negative value for the improvement of the hold characteristic of the memory cell.
The well structures in the DRAM are classified into two types, a twin well and a triple well. In the twin well type, the substrate potential of an N-channel transistor in a peripheral circuit (a logic section) on a P-type substrate is set to VBB, because the substrate potential is common to that of a memory cell section. On the contrary, in the triple well type, the substrate potential of an N-channel transistor in the peripheral circuit is electrically isolated from the substrate potential of the memory cell section. Therefore, both of the substrate potentials can be determined individually and independently. While the substrate potential of the memory cell section is the potential VBB, the substrate potential of the peripheral circuit is the GND potential.
The constant current source circuit 10 shown in FIG. 1 is formed in a peripheral circuit. In the triple well type, the substrate potential of the N-channel transistor in the peripheral circuit is the GND potential and not affected by the VBB noise. That is, the VBB noise has no influence in the constant current source circuit 10 shown in FIG. 1. On the other hand, in a twin well type, it is necessary to remove the VBB noise. Adoption of the twin well type reduces the manufacturing cost, compared with the triple well type.
FIG. 5 is a cross sectional view showing an example of N-channel MOS transistors. The N-channel transistor 31 is formed in a P-type substrate 34. A junction capacitance Cj is formed between an N-type diffusion layer 35 of the N-channel transistor 31 and the P substrate 34. The junction capacitance Cj is about 0.5 fF (femto-farads, 1xc3x9710xe2x88x9215 F) per square micrometer of the N diffusion layer 35. As shown in FIG. 5, the P-type substrate 34 is connected to a node with the VBB substrate potential via a sub-contacts Sc.
FIG. 6 illustrates an inverter 40 which is composed of a P-channel transistor 41 and an N-channel transistor 32. Here, it is supposed that the N-channel transistor 32 in the inverter 40 is shown in FIG. 5. When the inverter 40 operates, the potential at a node a changes. At this time, the potential VBB of the P-type substrate 34 locally receives a high frequency noise through coupling to an N-type diffusion layer 36a where a signal is supplied from the P substrate 34 shown in FIG. 5. As a result, the VBB potential for the N-channel transistor 31 will be affected by the noise.
Similarly, the two transistors M1 and M2 in the constant current source circuit 10 shown in FIG. 1 are laid out in the same manner as the N-channel transistor 31 shown in FIG. 5 and will be affected by the high frequency VBB noise. Also, the nodes B and D shown in FIGS. 1 and 3 are coupled to the VBB potential by the junction capacitance of the N diffusion layer and the capacitance of the wiring line, as well as a parasitic capacitance of the resistor R1. Therefore, when the high frequency VBB noise which has a frequency higher than a frequency for a time constant of the parasitic capacitance of the resistor R1 and the resistor R1, the potentials of the nodes B and D may fluctuate at substantially the same amplitude and phase as those of the high frequency VBB noise (coupling noise).
On the other hand, the source of the transistor M1 is connected directly to the GND potential so that the potential at the source is hardly affected by the VBB noise. Accordingly, the gatexe2x80x94source voltage VGS of the transistor M1 (in this example, the gate is connected to the node B and the source is connected to the GND potential) is varied depending on the VBB noise. However, the gatexe2x80x94source voltage VGS of the transistor M2 (in this example, the gate is connected the node B and the source is connected to the node D) fluctuates at the same phase as the VBB noise so that the potential VGS does not change. As shown in FIG. 2, the sub-threshold characteristic curve of the transistor M1 changes in an exponential function with the change of the voltage VGS. Hence, if the voltage VGS is increased by the VBB noise, an exponentially increased current flows. This causes the average potential of the node B to drop lower, compared with no application of the VBB noise. Accordingly, the voltage VGS of the transistor M2 will be smaller, since the potentials of the nodes B and D fluctuate at the same phase as the VBB noise, compared with no introduction of the VBB noise. When the VBB noise is present, the current I2 is decreased.
In this way, when the VBB potential receives a high frequency noise, a difference in the average current between the two transistors M1 and M2 is caused. As a result, the output current Iout will be smaller. In the reference potential generating circuit 20 shown in FIG. 3, the output voltage Vout will also be decreased.
When the VBB potential is changed locally as shown in FIGS. 5 and 6, the VBB noise has as a higher frequency as over a few gigahertz (1xc3x97109 GHz). Also, in case that the semiconductor device is operated in synchronous with a clock signal supplied externally, the VBB potential may receive a noise of the same frequency. The frequency ranges from some hundreds kilohertz to some hundreds megahertz.
In conjunction with the above description, a semiconductor biasing circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 2-115911). In this reference, a source of a P-channel enhancement FET (Q3) is connected to a DC potential VDD. An N-channel enhancement FET (Q1) is connected at its drain to a drain of the P-channel enhancement FET (Q3) and at its source to a common potential point. A P-channel enhancement FET (Q4) is connected at its source to the DC potential VDD. An N-channel enhancement FET (Q2) is connected at its drain to a drain of the P-channel enhancement FET (Q4) and at its source to the common potential point via a resistor R1. A P-channel enhancement FET (Q5) is connected at its source to the DC potential VDD and its drain to another DC potential VSS, which is lower than the DC potential VDD, via a load resistor RL. A P-channel enhancement FET (Q6) is connected at its source to the DC potential VDD and at its drain to the common potential point. A first control circuit connects the drain of the N-channel enhancement FET (Q1) to the gates of the N-channel enhancement FETs (Q1 and Q2) and the gate of the P-channel enhancement FET (Q6), respectively. A second control circuit connects the drain of the P-channel enhancement FET (Q4) to the gates of the P-channel enhancement FETs (Q4, Q3 and Q5), respectively. A constant current circuit is interposed between the common potential point and the other potential VSS.
Also, a constant current circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 4-097405). In this reference, the constant current circuit is composed of a band gap circuit including a resistor and a MOS transistor for giving a band gap potential between two MOS transistors, and a current mirror circuit for supplying constant currents to the two MOS transistors. An output added to the current mirror circuit is fed back as a part of the band gap potential.
Also, a constant current circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 5-191166). In this reference, a MOS transistor M1 is connected at its source to the ground potential and at its drain to its gate via a resistor R and to a source of a MOS transistor M3. A MOS transistor M2 is connected at its source to the ground potential, and at its drain to a drain of the source of the MOS transistor M4. The MOS transistors M1 and M2 have the same ability. The MOS transistors M3 and M4 are used in a current mirror circuit which drives the MOS transistors M1 and M2. The MOS transistors M3 and M4 have an ability ratio of M3:M4=k:1. In other words, the MOS transistors M1 and M2 operates in a current ratio of K:1. As a result, a drive current is not influenced by a power supply potential change and a threshold potential change.
Also, a constant current circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-322163). In this reference, a first potential which is generated from a potential generating circuit and is proportional to temperature is supplied to an inversion input terminal of a differential amplifier circuit while a noise component is removed from the first potential by an external capacitor. A reference potential which does not have a temperature characteristic is supplied to a non-inversion input terminal of the differential amplifier circuit while a noise component is removed from the reference potential by an external capacitor. Thus, a second potential is generated from the differential amplifier circuit and a current mirror circuit generates a reference current which is proportional to temperature, based on the second potential.
Therefore, an object of the present invention is to provide a semiconductor device with a constant current source circuit which can hardly be affected by any noise.
In order to achieve an aspect of the present invention, a semiconductor device with a constant current source circuit includes a current mirror circuit, third and fourth transistors, a first resistor and a potential change transferring section. The current mirror circuit includes first and second transistors which are connected to a line of a power supply potential and supply first and second currents, respectively. Each of the third and fourth transistors has a control electrode and first and second electrodes. The control electrode is operatively coupled to a first potential. The first electrode and the control electrode in the third transistor are connected to a first node, and the control electrode of the fourth transistor is connected to the first node. The third and fourth transistors receive the first and second currents at the first electrodes from the current mirror circuit, respectively. The first resistor is connected between the second electrode of the fourth transistor and a second node. The potential change transferring section is connected to a second potential and the second node such that a change of potential difference between the first potential and the second potential is transferred to the second electrodes of the third and fourth transistors.
The potential change transferring section is provided to hold a potential difference between the control electrode and the second electrode in each of the third and fourth transistors when the potential difference between the first potential and the second potential changes.
Also, the second electrode of the third transistor is connected directly to the second node, and the potential change transferring section may include a second resistor connected between the second node and the second potential. In this case, the potential change transferring section further includes a first capacitor connected between the second node and the second potential. A combination of the first capacitor and the second resistor functions as a low pass filter with a cut-off frequency of 1/{2xcfx80R2(C(A)+Co)☆, where R2 is a resistance of the second resistor, C(A) is a parasitic capacitance of the second node, and Co is a junction capacitance between a diffusion layer and a substrate on which the first to fourth transistors are formed. Also, the diffusion layer is formed to surround a region where the third and fourth transistors are formed.
Also, the potential change transferring section may include a low pass filter connected between the second node and the second potential.
Also, the potential change transferring section may include a third resistor connected between the second electrode of the third transistor and the second node, the second node being connected directly to the second potential. In this case, the third resistor has a resistance which meets a relation of (I2R1xe2x88x92I1R3)=constant, where I1 and I2 are the first and second currents, R1 is a resistance of the first resistor and R3 is a resistance of the third resistor.
Also, the potential change transferring section may include a fourth resistor connected between the second electrode of the third transistor and the second node, a second capacitor connected between the first potential and the second electrode of the fourth transistor, and a third capacitor connected between the first potential and the second electrode of the third transistor, the second node being connected directly to the second potential. In this case, R4C3=R1C2, where R4 is a resistance of the fourth resistor, C3 and C2 are capacitances of the third and second capacitors, respectively, and R1 is a resistance of the first resistor. Also, the second capacitor is a parasitic capacitor to the second electrode of the fourth transistor.
In order to achieve another aspect of the present invention, a constant current source circuit includes first to fourth transistors, a first resistor and a holding section. The first transistor has a source connected to a power supply line, and a gate and drain. The second transistor has a source connected to the power supply line, a gate connected to the gate of the first transistor and a drain of the second transistor. The third transistor has a drain connected directly to the drain of the first transistor and a gate of the third transistor via a first node, and a source connected to a second node. The fourth transistor has a drain connected directly to the drain of the second transistor, a gate connected to the gate of the third transistor via the first node, and a source, the third and fourth transistors being operatively coupled to a first potential. The first resistor is connected between the source of the fourth transistor and a second node which is operatively coupled to a second potential. The holding section holds a potential difference between the gate and the source in each of the third and fourth transistors when the potential difference between the first potential and the second potential changes.
The holding section may include a second resistor connected between the second node and the second potential. In this case, the holding section may further include a first capacitor connected between the second node and the second potential. A combination of the first capacitor and the second resistor functions as a low pass filter with a cut-off frequency of 1/{2xcfx80R2(C(A)+Co)}, where R2 is a resistance of the second resistor, C(A) is a parasitic capacitance of the second node, and Co is a junction capacitance between a diffusion layer and a substrate on which the first to fourth transistors are formed. Also, the diffusion layer is desirably formed to surround a region where the third and fourth transistors are formed.
Also, the holding section may include a third resistor interposed between the source of the third transistor and the second node, the second node being connected directly to the second potential.
Also, the holding section may include a fourth resistor interposed between the source of the third transistor and the second node, a second capacitor connected between the first potential and the source of the fourth transistor, and a third capacitor connected between the first potential and the source of the third transistor, the second node being connected directly to the second potential. In this case, R4C3=R1C2, where R4 is a resistance of the fourth resistor, C3 and C2 are capacitances of the third and second capacitors, respectively, and R1 is a resistance of the first resistor.